SPIDR4 register map reference
This contains a list of the SPIDR4 registers. Please note that most functions are directly controlled by the principal application, and it is seldom required to directly address these registers. In addition it may interfere with normal operation or may even corrupt the system.
Note: The base address is 0x43c00000, all offsets are with respect to this address.
GIT_HASH
| Alias |
Bits |
Value |
Description |
| GIT_HASH |
31:0 |
|
Git hash of the current firmware |
Fan_Control
| Alias |
Bits |
Value |
Description |
| Fan_Control |
15:0 |
|
Fan speed control |
Fan_read
| Alias |
Bits |
Value |
Description |
| Fan_read |
31:0 |
|
Fan speed readback |
macSrc1Msb
| Offset | 0020h |
|---|
| Record | eth_config_type |
|---|
| Alias |
Bits |
Value |
Description |
| macSrc1Msb |
31:0 |
|
MSB bits (47 downto 16) of the MAC address of the first SFP (J33) |
macSrc1Lsb
| Offset | 0024h |
|---|
| Record | eth_config_type |
|---|
| Alias |
Bits |
Value |
Description |
| macSrc1Lsb |
15:0 |
|
LSB bits (15 downto 0) of the MAC address of the first SFP (J33) |
macSrc2Msb
| Offset | 0028h |
|---|
| Record | eth_config_type |
|---|
| Alias |
Bits |
Value |
Description |
| macSrc2Msb |
31:0 |
|
MSB bits (47 downto 16) of the MAC address of the second SFP (J34) |
macSrc2Lsb
| Offset | 002Ch |
|---|
| Record | eth_config_type |
|---|
| Alias |
Bits |
Value |
Description |
| macSrc2Lsb |
15:0 |
|
LSB bits (15 downto 0) of the MAC address of the second SFP (J34) |
macDst1Msb
| Offset | 0030h |
|---|
| Record | eth_config_type |
|---|
| Alias |
Bits |
Value |
Description |
| macDst1Msb |
31:0 |
|
MSB bits (47 downto 16) of the MAC address of the PC connected to the first SFP (J33) |
macDst1Lsb
| Offset | 0034h |
|---|
| Record | eth_config_type |
|---|
| Alias |
Bits |
Value |
Description |
| macDst1Lsb |
15:0 |
|
LSB bits (15 downto 0) of the MAC address of the PC connected to the first SFP (J33) |
macDst2Msb
| Offset | 0038h |
|---|
| Record | eth_config_type |
|---|
| Alias |
Bits |
Value |
Description |
| macDst2Msb |
31:0 |
|
MSB bits (47 downto 16) of the MAC address of the PC connected to the second SFP (J34) |
macDst2Lsb
| Offset | 003Ch |
|---|
| Record | eth_config_type |
|---|
| Alias |
Bits |
Value |
Description |
| macDst2Lsb |
15:0 |
|
LSB bits (15 downto 0) of the MAC address of the PC connected to the second SFP (J34) |
ipSrc1
| Offset | 0040h |
|---|
| Record | eth_config_type |
|---|
| Alias |
Bits |
Value |
Description |
| ipSrc1 |
31:0 |
|
IP address of the first SFP(J33) |
ipSrc2
| Offset | 0044h |
|---|
| Record | eth_config_type |
|---|
| Alias |
Bits |
Value |
Description |
| ipSrc2 |
31:0 |
|
IP address of the second SFP(J34) |
ipDst1
| Offset | 0048h |
|---|
| Record | eth_config_type |
|---|
| Alias |
Bits |
Value |
Description |
| ipDst1 |
31:0 |
|
IP address of the PC connected to the first SFP(J33) |
ipDst2
| Offset | 004Ch |
|---|
| Record | eth_config_type |
|---|
| Alias |
Bits |
Value |
Description |
| ipDst2 |
31:0 |
|
IP address of the PC connected to the second SFP(J34) |
portSrc1
| Offset | 0050h |
|---|
| Record | eth_config_type |
|---|
| Alias |
Bits |
Value |
Description |
| portSrc1 |
31:0 |
|
Port number of the first SFP(J33) |
portSrc2
| Offset | 0054h |
|---|
| Record | eth_config_type |
|---|
| Alias |
Bits |
Value |
Description |
| portSrc2 |
31:0 |
|
Port number of the second SFP(J34) |
portDst1
| Offset | 0058h |
|---|
| Record | eth_config_type |
|---|
| Alias |
Bits |
Value |
Description |
| portDst1 |
31:0 |
|
Port number of the PC connected to the first SFP(J33) |
portDst2
| Offset | 005Ch |
|---|
| Record | eth_config_type |
|---|
| Alias |
Bits |
Value |
Description |
| portDst2 |
31:0 |
|
Port number of the PC connected to the second SFP(J34) |
sfpConfig
| Alias |
Bits |
Value |
Description |
| sfp |
0 |
0 |
Data will be sent on both SFP interfaces |
| 1 |
Data will be sent only on first SFP(J33) |
emulatorCtrl
| Alias |
Bits |
Value |
Description |
| start_stop |
0 |
0 |
Stop generating dummy data |
| 1 |
Generating dummy data |
| reset |
1:1 |
0 |
Emulator does not hold at reset |
| 1 |
Emulator holds at reset |
SC_TX_Data
| Offset | 0068h |
|---|
| Record | SC_reg_out |
|---|
| Alias |
Bits |
Value |
Description |
| SC_TX_Data |
31:0 |
|
Slow-control TX fifo interface, wr_en triggered by the strobe |
SC_RX_Data
| Offset | 006Ch |
|---|
| Record | SC_reg_in |
|---|
| Alias |
Bits |
Value |
Description |
| SC_RX_Data |
31:0 |
|
Slow-control RX fifo interface, rd_en triggered by the strobe |
SC_CTRL
| Offset | 0070h |
|---|
| Record | SC_reg_out |
|---|
| Alias |
Bits |
Value |
Description |
| SC_TX_transmit |
0 |
0 |
Start transmit statemachine |
| SC_TX_flush |
1 |
0 |
flush the TX fifo |
| SC_TX_error_ack |
2 |
0 |
TX_error_ack |
| SC_local_loopback |
3 |
0 |
local_loopback |
| SC_TX_polarity |
4 |
0 |
TX_polarity |
| SC_RX_reset_statemachine |
5 |
0 |
Resets RX statemachine and flushes the RX fifo |
| SC_RX_polarity |
6 |
0 |
RX_polarity |
| SC_RX_byteswap |
7 |
0 |
RX_byteswap |
| SC_RX_rd_en |
8 |
0 |
RX_rd_en |
| SC_MAN_TPX_Reset |
9 |
0 |
Perform a manual reset of the Timepix4 |
| SC_MAN_T0_SYNC |
10 |
0 |
Perform a manual T0 Sync pulse |
| SC_MAN_SHUTTER |
11 |
0 |
Manual TPX shutter signal |
| SC_CLOCK_FREQ |
13:12 |
0 |
Set the SC Clock to 40MHz(00), 20MHz(01) or 5MHz(10) - outdated, always uses 41MHz |
| SC_TX_byteswap |
14 |
0 |
TX_byteswap |
| SC_RX_LEN |
24:15 |
|
Number of expected RX bytes including headers except the sync_header byte |
SC_STATUS
| Offset | 0074h |
|---|
| Record | SC_reg_in |
|---|
| Alias |
Bits |
Value |
Description |
| SC_RX_empty |
0 |
0 |
RX_empty |
| SC_RX_full |
1 |
0 |
RX_full |
| SC_TX_empty |
2 |
0 |
TX_empty |
| SC_TX_full |
3 |
0 |
TX_full |
| SC_TX_statemachine_busy |
4 |
0 |
TX_statemachine_busy |
| SC_TX_statemachine_error |
5 |
0 |
TX_statemachine_error |
Delay_control
| Offset | 0078h |
|---|
| Record | Delay_control |
|---|
| Alias |
Bits |
Value |
Description |
| Channel_A |
9:0 |
|
Channel A delay, 5ps increments |
| Channel_B |
25:16 |
|
Channel B delay, 5ps increments |
FPGA_BITFILE_DATE
| Alias |
Bits |
Value |
Description |
| FPGA_BITFILE_DATE |
31:0 |
|
ddddd_MMMM_yyyyyy_hhhhh_mmmmmm_ssssss |
CH0_Transceiver_control_write
| Offset | 0080h |
|---|
| Record | Transceiver_ctrl_write |
|---|
| Alias |
Bits |
Value |
Description |
| CH0_RESET |
0 |
|
Reset the transceiver block |
| CH0_BLOCKSYNC_RESET |
1 |
|
Reset the word alignment block |
| CH0_POLARITY |
2 |
|
Change the incoming signal polarity |
| CH0_CDR_HOLD |
3 |
|
Stop the clock recovery from slipping |
| CH0_PRBS_MODE |
6:4 |
000 |
PRBS check is off |
| 001 |
PRBS-7 check is on |
| 010 |
PRBS-15 check is on |
| 011 |
PRBS-23 check is on |
| 100 |
PRBS-31 check is on |
| CH0_PRBS_CNT_RESET |
7 |
|
Reset the PRBS error counter |
| CH0_DATA_OUT_ENABLE |
8 |
|
enable the data transmission |
CH0_Transceiver_control_read
| Offset | 0084h |
|---|
| Record | Transceiver_ctrl_read |
|---|
| Alias |
Bits |
Value |
Description |
| CH0_FSM_RESET_DONE |
0 |
|
GTX statemachines reset done |
| CH0_RX_RESET_DONE |
1 |
|
GTX reset done |
| CH0_CPLL_LOCK |
2 |
|
The CPLL is locked |
| GT0_RX_MMCM_LOCK |
3 |
|
The transceiver MMCM is locked |
| CH0_BLOCKSYNC_LOCK |
4 |
|
The blocksync lock is aligned with the header |
| CH0_RX_PRBS_ERR_CNT |
23:8 |
|
PRBS error counter |
CH1_Transceiver_control_write
| Offset | 0088h |
|---|
| Record | Transceiver_ctrl_write |
|---|
| Alias |
Bits |
Value |
Description |
| CH1_RESET |
0 |
|
Reset the transceiver block |
| CH1_BLOCKSYNC_RESET |
1 |
|
Reset the word alignment block |
| CH1_POLARITY |
2 |
|
Change the incoming signal polarity |
| CH1_CDR_HOLD |
3 |
|
Stop the clock recovery from slipping |
| CH1_PRBS_MODE |
6:4 |
000 |
PRBS check is off |
| 001 |
PRBS-7 check is on |
| 010 |
PRBS-15 check is on |
| 011 |
PRBS-23 check is on |
| 100 |
PRBS-31 check is on |
| CH1_PRBS_CNT_RESET |
7 |
|
rest the prbs error counter |
| CH1_DATA_OUT_ENABLE |
8 |
|
Enable the data transmission |
CH1_Transceiver_control_read
| Offset | 008Ch |
|---|
| Record | Transceiver_ctrl_read |
|---|
| Alias |
Bits |
Value |
Description |
| CH1_FSM_RESET_DONE |
0 |
|
GTX statemachines reset done |
| CH1_RX_RESET_DONE |
1 |
|
GTX reset done |
| CH1_CPLL_LOCK |
2 |
|
The CPLL is locked |
| GT1_RX_MMCM_LOCK |
3 |
|
The transceiver MMCM is locked |
| CH1_BLOCKSYNC_LOCK |
4 |
|
The blocksync lock is aligned with the header |
| CH1_RX_PRBS_ERR_CNT |
23:8 |
|
PRBS error counter |
Shutter_monitor
| Offset | 0090h |
|---|
| Record | Shutter_ctrl_read |
|---|
| Alias |
Bits |
Value |
Description |
| auto_trigger_busy |
0 |
|
Indicates the auto-shutter is busy |
Shutter_counter
| Offset | 0094h |
|---|
| Record | Shutter_ctrl_read |
|---|
| Alias |
Bits |
Value |
Description |
| shutter_counter |
31:0 |
|
Number of shutters (also external) |
T0_sync_counter
| Offset | 0098h |
|---|
| Record | Shutter_ctrl_read |
|---|
| Alias |
Bits |
Value |
Description |
| T0_sync_counter |
31:0 |
|
Number of T0 syncs (also external) |
Shutter_control
| Offset | 009Ch |
|---|
| Record | Shutter_ctrl_write |
|---|
| Alias |
Bits |
Value |
Description |
| enable_shutter_circuit |
0 |
|
Enable the shutter generator |
| start_auto_trigger |
1 |
|
Start the auto-shutter |
| stop_auto_trigger |
2 |
|
Stop the auto-shutter |
| reset_shutter_counter |
3 |
|
Reset the shutter counter |
| reset_T0_counter |
4 |
|
Reset the T0 sync counter |
| Trigger_T0 |
5 |
|
Trigger a 100us T0 sync pulse |
| Shutter_source |
7:6 |
00 |
The shutter is controlled through the Zynq register map |
| 01 |
The shutter is controlled through the shutter generator |
| 10 |
The shutter is connected to the external HDMI input |
| 11 |
The external HDMI input (rising edge) triggers the auto-shutter |
| T0_source |
9:8 |
00 |
The T0 is controlled through the Zynq register map |
| 01 |
The T0 is a 100us pulse triggered by 'Trigger_T0' |
| 10 |
The T0 is connected to the external HDMI input |
| Busy_out_source |
11:10 |
00 |
The HDMI Busy output is '0' |
| 01 |
The HDMI Busy output is auto_trigger_busy |
| 10 |
The HDMI Busy output is a copy of T0_sync |
| 11 |
The HDMI Busy output is a copy of Shutter |
| HDMI_test_enable |
12 |
|
Set all HDMI channels to output 40MHz (intended for PCB testing) |
Shutter_frequency
| Offset | 00A0h |
|---|
| Record | Shutter_ctrl_write |
|---|
| Alias |
Bits |
Value |
Description |
| Shutter_frequency |
31:0 |
|
Shutter frequency in 25ns increments |
Shutter_period
| Offset | 00A4h |
|---|
| Record | Shutter_ctrl_write |
|---|
| Alias |
Bits |
Value |
Description |
| Shutter_period |
31:0 |
|
Shutter period in 25ns increments |
Shutter_number
| Offset | 00A8h |
|---|
| Record | Shutter_ctrl_write |
|---|
| Alias |
Bits |
Value |
Description |
| Shutter_number |
31:0 |
|
Number of shutter pulses |
Firmware_info
| Offset | 00ACh |
|---|
| Record | Firmware_info |
|---|
| Alias |
Bits |
Value |
Description |
| debug_mode |
0 |
|
Debug mode on or off |
| link_speed |
1 |
|
Serial link speed 2.56Gb (0) or 5.12Gb (1) |
| WR_firmware |
2 |
|
Firmware supports White Rabbit |
| MPX4_firmware |
3 |
|
Firmware supports Medipix4 |
Stats_control
| Offset | 0300h |
|---|
| Record | Statistics_write |
|---|
| Alias |
Bits |
Value |
Description |
| tpx4_stats_update |
0 |
|
Rising edge updates TPX4 packet counter registers and resets internal counters |
| tpx4_stats_sel_top |
1 |
|
Statistics_read registers show stats for the top (1) or bottom (0) half |
| tpx4_stats_sel |
4:2 |
000 |
Stats_ctrlpacket_counter shows the number of heartbeat packets (EoC=0xE0) |
| 001 |
Stats_ctrlpacket_counter shows the number of shutter rise packets (EoC=0xE1) |
| 010 |
Stats_ctrlpacket_counter shows the number of shutter fall packets (EoC=0xE2) |
| 011 |
Stats_ctrlpacket_counter shows the number of T0 sync packets (EoC=0xE3) |
| 100 |
Stats_ctrlpacket_counter shows the number of other control packets (EoC=0xE4/0xE5/0xEA/0xF0-3) |
| 101 |
Stats_ctrlpacket_counter shows the number of invalid control packets |
| tpx4_stats_disable |
5 |
|
If 1 disables the statistics module and resets the counters. |
Stats_hitpacket_counter_low
| Offset | 0304h |
|---|
| Record | Statistics_read |
|---|
| Alias |
Bits |
Value |
Description |
| hits_low |
31:0 |
|
Bits [31:0] of the hit counter at the last rising edge of tpx4_stats_update |
Stats_hitpacket_counter_high
| Offset | 0308h |
|---|
| Record | Statistics_read |
|---|
| Alias |
Bits |
Value |
Description |
| hits_high |
17:0 |
|
Bits [49:32] of the hit counter at the last rising edge of tpx4_stat_update |
Stats_ctrlpacket_counter
| Offset | 030Ch |
|---|
| Record | Statistics_read |
|---|
| Alias |
Bits |
Value |
Description |
| ctrls |
31:0 |
|
Value of the control packet counter selected by tpx4_stats_sel at the last rising edge of tpx4_stats_update |